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Sheet目录3881

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2004 Microchip Technology Inc.

DS30491C-page 333

PIC18F6585/8585/6680/8680

23.7

Message Reception

23.7.1

RECEIVING A MESSAGE

Of all receive buffers, the MAB is always committed to

receiving the next message from the bus. The MCU

can access one buffer while the other buffer is available

for message reception, or holding a previously received

message.

When a message is moved into either of the receive

buffers, the associated RXFUL bit is set. This bit must

be cleared by the MCU when it has completed process-

ing the message in the buffer in order to allow a new

message to be received into the buffer. This bit

provides a positive lockout to ensure that the firmware

has finished with the message before the module

attempts to load a new message into the receive buffer.

If the receive interrupt is enabled, an interrupt will be

generated to indicate that a valid message has been

received.

Once a message is loaded into any matching buffer,

user firmware may determine exactly what filter caused

this reception by checking the filter hit bits in the

RXBnCON or BnCON registers. In Mode 0, FILHIT<3:0>

of RXBnCON serve as filter hit bits. In Mode 1 and 2,

FILHIT<4:0> of BnCON serve as filter hit bits. The same

registers also indicate whether the current message is

RTR frame or not. A received message is considered a

standard identifier message if the EXID bit in RXBnSIDL

or the BnSIDL register is cleared. Conversely, a set

EXID bit indicates an extended identifier message. If the

received message is a standard identifier message, user

firmware needs to read the SIDL and SIDH registers. In

the case of an extended identifier message, firmware

should read the SIDL, SIDH, EIDL and EIDH registers. If

the RXBnDLC or BnDLC register contain non-zero data

count, user firmware should also read the corresponding

number of data bytes by accessing the RXBnDm or

BnDm registers. When a received message is RTR and

if the current buffer is not configured for automatic RTR

handling, user firmware must take appropriate action

and respond manually.

Each receive buffer contains RXM bits to set special

Receive modes. In Mode 0, RXM<1:0> bits in

RXBnCON define a total of four Receive modes. In

Mode 1 and 2, RXM1 bit in combination with the EXID

mask and filter bit define the same four Receive

modes. Normally, these bits are set to ‘00’ to enable

reception of all valid messages as determined by the

appropriate acceptance filters. In this case, the deter-

mination of whether or not to receive standard or

extended messages is determined by the EXIDE bit in

the Acceptance Filter register. In Mode 0, if the RXM

bits are set to ‘01’ or ‘10’, the receiver will accept only

messages with standard or extended identifiers,

respectively. If an acceptance filter has the EXIDE bit

set such that it does not correspond with the RXM

mode, that acceptance filter is rendered useless. In

Mode 1 and 2, setting EXID in the SIDL Mask register

will ensure that only standard or extended identifiers

are received. These two modes of RXM bits can be

used in systems where it is known that only standard or

extended messages will be on the bus. If the RXM bits

are set to ‘11’ (RXM1 = 1 in Mode 1 and 2), the buffer

will receive all messages regardless of the values of

the acceptance filters. Also, if a message has an error

before the end of frame, that portion of the message

assembled in the MAB before the error frame, will be

loaded into the buffer. This mode may serve as a valu-

able debugging tool for a given CAN network. It should

not be used in an actual system environment as the

actual system will always have some bus errors and all

nodes on the bus are expected to ignore them.

In Mode 1 and 2, when a programmable buffer is

configured as a transmit buffer and one or more accep-

tance filters are associated with it, all incoming mes-

sages matching this acceptance filter criteria will be

discarded. To avoid this scenario, user firmware must

make sure that there are no acceptance filters associ-

ated with a buffer configured as a transmit buffer.

23.7.2

RECEIVE PRIORITY

When in Mode 0, RXB0 is the higher priority buffer and

has two message acceptance filters associated with it.

RXB1 is the lower priority buffer and has four acceptance

filters associated with it. The lower number of acceptance

filters makes the match on RXB0 more restrictive and

implies a higher priority for that buffer. Additionally, the

RXB0CON register can be configured such that if RXB0

contains a valid message and another valid message is

received, an overflow error will not occur and the new

message will be moved into RXB1 regardless of the

acceptance criteria of RXB1. There are also two

programmable acceptance filter masks available, one for

each receive buffer (see Section 4.5).

Note:

The entire contents of the MAB are moved

into the receive buffer once a message is

accepted. This means that regardless of

the

type

identifier

(standard

extended) and the number of data bytes

received, the entire receive buffer is over-

written with the MAB contents. Therefore,

the contents of all registers in the buffer

must be assumed to have been modified

when any message is received.

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